【百家大講堂】第236期：AI時(shí)代2.5/3D技術(shù)

來源：發(fā)布日期：2019-09-11

講座題目：AI時(shí)代2.5/3D技術(shù) Future 2.5/3D Technologies in AI Era

報(bào) 告人：小柳光正 Mitsumasa Koyanagi（教授/GINTI中心主任）

時(shí) 　間：2019年9月13日(周五)10:00-11：30

地　點(diǎn)：中關(guān)村校區(qū)信息實(shí)驗(yàn)樓205會議室

主辦單位：研究生院、信息與電子學(xué)院

報(bào)名方式：登錄北京理工大學(xué)微信企業(yè)號---第二課堂---課程報(bào)名中選擇“【百家大講堂】第236期：AI時(shí)代2.5/3D技術(shù)”

【主講人簡介】

小柳光正(Mitsumasa Koyanagi)教授1947年生于日本北海道,，并于1974年獲得日本東北大學(xué)博士學(xué)位,。1974年至1980年于日立的中央研究實(shí)驗(yàn)室發(fā)明了世界上第一款商業(yè)化的三維堆疊電容型動態(tài)隨機(jī)存取存儲器；1985年至1988年,，他加入了位于美國加州的帕羅奧多研究中心,，從事亞微米CMOS器件、多晶硅薄膜晶體管等的研究；1988年,，加入廣島大學(xué),，從事亞微米器件加工及表征、器件建模,、多晶硅TFT器件,、三維集成技術(shù)、光學(xué)互連以及并行計(jì)算系統(tǒng)研究,，并于1992年成功制備出柵長70nm的當(dāng)時(shí)最小尺寸的MOS管,，相關(guān)研究發(fā)表于當(dāng)年的IEDM；1989年,，在國際上首次提出基于晶圓鍵合工藝以及穿透硅通孔技術(shù)為基礎(chǔ)的三維集成技術(shù)并一直在該領(lǐng)域處于國際領(lǐng)先地位,，所帶領(lǐng)的課題組已經(jīng)在IEDM上發(fā)表相關(guān)研究論文10余篇；在三維集成以及光學(xué)互連領(lǐng)域有20余年的研究經(jīng)驗(yàn),，發(fā)表了300余篇署名期刊論文,，國際會議受邀演講達(dá)到100余次，為IEEE協(xié)會Fellow,，日本應(yīng)用物理學(xué)會Fellow,，先后被IEEE協(xié)會、日本應(yīng)用物理協(xié)會,、日本文部科學(xué)省等授予多項(xiàng)獎勵,。目前為日本東北大學(xué)教授、GINTI中心主任,。

Mitsumasa Koyanagi (M86-M’90-F’97) was born in Hokkaido, Japan. He received the B.S. degree in electrical engineering from Muroran Institute of Technology, Muroran, Japan, in 1969 and the M.S. and Ph.D degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1971 and 1974, respectively.

From 1974 to 1980, he was with Central Research laboratory, Hitachi Ltd., where he invented a stacked capacitor dynamic random access memory (DRAM) memory cell, which was the first commercialized 3-D large-scale integration (LSI) system. From 1980 to 1985, he was with the Device Development Center, Hitachi Ltd. From 1985 to 1988, he joined the Xerox Palo Alto Research Center, Palo Alto, CA, where he worked on the research and development of submicrometer complementary metal-oxide-semiconductor (CMOS) devices, polysilicon thin-film transistors, and the design of analog/digital LSIs.

In 1988, he joined the Research Center for Integrated Systems, Hiroshima University, Hiroshima, as a Professor, where he worked on scaled MOS devices, 3-D integration technology, optical interconnections, and parallel computer systems specific for scientific computation. He fabricated the smallest MOS transistor with a gate length of 70nm in 1992. He proposed a 3-D integration technology based on wafer-to-wafer bonding for the first time in 1989.

Since 1994, he has been a Professor with Tohoku University(the Department of Machine Intelligence and Systems Engineering, the Department of Bioengineering and Robotics, and, currently, the New Industry Creation Hatchery Center), where his current interests are Nano-CMOS devices, memory devices, low-voltage and low-power integrated circuits, new intelligent memory for parallel processor systems, 3-D integration technology, optical interconnections, parallel computer systems specific for science computation, real-time image processing systems and artificial retina chips, retinal prosthesis, and brain-implant devices and brainlike computer systems. He has been researching 3-D integration technology and optical interconnection for more than 20 years.

Dr. Koyanagi was the receipt of the 2006 IEEE Jun-ichi Nishizawa Medal, the 1996 IEEE Cledo Brunetti Award, the 2001 Award of Ministry of Education, Culture, Sports, Science and Technology, the 1994 Solid-State Devices and Materials Award, the 2004 Optoelectronic Technology Achievement Award(Japan Society of Applied Physics), and the 1990 Okouchi Prize.

【講座信息】

2.5/3D集成技術(shù)是未來適應(yīng)AI時(shí)代應(yīng)用的高性能,、低功耗、多功能超大規(guī)模集成電路與系統(tǒng)關(guān)鍵技術(shù)之一,。特別是隨著晶體管尺寸進(jìn)一步縮小至10nm以下帶來的諸如器件設(shè)計(jì)/制造成本攀升,、互連延遲等問題加劇，具備將在不同襯底材料上利用不同工藝節(jié)點(diǎn)技術(shù)制備的多種不同大小和功能的器件芯片等在同一硅晶圓上進(jìn)行3D異質(zhì)系統(tǒng)集成已逐漸成為延續(xù)摩爾定律的有效手段,。本次講座將在回顧2.5/3D集成技術(shù)發(fā)展現(xiàn)狀基礎(chǔ)上,，結(jié)合未來AI時(shí)代應(yīng)用需求對2.5/3D技術(shù)發(fā)展要求進(jìn)行解析和展望。

2.5/3D integration technology is the key for future LSIs with high-performance, low-power and multi-functionality in the future AI era. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology will be discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.